Microcontroller Ic

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ARM Microcontrollers - MCU Ultra-low-power Arm Cortex-M3 MCU 512 Kbytes of Flash 32 MHz CPU, MCD, USB, 2xOp

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TMS320F28035PN LQFP (80) 12.0 mm × 12.0 mm TMS320F28034PN LQFP (80) 12.0 mm × 12.0 mm TMS320F28033PN LQFP (80) 12.0 mm × 12.0 mm TMS320F28032PN LQFP (80) 12.0 mm × 12.0 mm TMS320F28031PN LQFP (80) 12.0 mm × 12.0 mm TMS320F28030PN LQFP (80) 12.0 mm × 12.0 mm TMS320F28035PAG TQFP (64) 10.0 mm × 10.0 mm TMS320F28034PAG TQFP (64) 10.0 mm × 10.0 mm TMS320F28033PAG TQFP (64) 10.0 mm × 10.0 mm TMS320F28032PAG TQFP (64) 10.0 mm × 10.0 mm TMS320F28031PAG TQFP (64) 10.0 mm × 10.0 mm TMS320F28030PAG TQFP (64) 10.0 mm × 10.0 mm TMS320F28035RSH VQFN (56) 7.0 mm × 7.0 mm TMS320F28034RSH VQFN (56) 7.0 mm × 7.0 mm TMS320F28033RSH VQFN (56) 7.0 mm × 7.0 mm TMS320F28032RSH VQFN (56) 7.0 mm × 7.0 mm TMS320F28031RSH VQFN (56) 7.0 mm × 7.0 mm TMS320F28030RSH VQFN (56) 7.0 mm × 7.0 mm (1) For more information on these devices, see Mechanical, Packaging, and Orderable Information. www.ti.com TMS320F28030, TMS320F28030-Q1, TMS320F28031, TMS320F28031-Q1, TMS320F28032 TMS320F28032-Q1, TMS320F28033, TMS320F28033-Q1, TMS320F28034, TMS320F28034-Q1 TMS320F28035, TMS320F28035-Q1 SPRS584P – APRIL 2009 – REVISED JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TMS320F28030 TMS320F28030-Q1 TMS320F28031 TMS320F28031-Q1 TMS320F28032 TMS320F28032-Q1 TMS320F28033 TMS320F28033-Q1 TMS320F28034 TMS320F28034-Q1 TMS320F28035 TMS320F28035-Q1 3.1 Functional Block Diagram The Functional Block Diagram shows the functional block diagram for the device. 3 External Interrupts M0 SARAM 1K × 16 (0-wait) 16-Bit Peripheral Bus SPISTEx M1 SARAM 1K × 16 (0-wait) eCAN (32-mail box) SCI (4L FIFO) ePWM SPI (4L FIFO) I2C (4L FIFO) LIN HRPWM 32-Bit Peripheral Bus GPIO MUX C28x 32-Bit CPU A7:0 B7:0 PIE CPU Timer 0 CPU Timer 1 CPU Timer 2 TCK TDI TMS TDO TRST OSC1, OSC2, Ext, PLL, LPM, WD XCLKIN X2 XRS 32-Bit Peripheral Bus (CLA-Accessible) eCAPECAPx EPW MxA EPW MxB CANRXx CANTXx SDAx SCLx SPISIMO x SPISOMIx SPICLKx COMP1OUT SCIRXDx GPIO Mux LPM Wakeup CLA ADC Boot-ROM 8K × 16 (0-wait) SARAM 4K/6K/8K × 16 (CLA Only on 28033 and 28035) (0-wait) Secure LINARX LINATX COMP COMP1A COMP1B COMP2A COMP2B COMP3A COMP3B COMP2OUT COMP3OUT eQEP SCITXDx EQ EPxA EQ EPxB EQE PxI EQEPxS X1 GPIO MUX AIO MUX From COMP1OUT, COMP2OUT, COMP3OUT VREG POR/ BOR Memory Bus CLA Bus Memory Bus Memory Bus TZx PSWD FLASH 16K/32K/64K × 16 Secure OTP/Flash Wrapper OTP 1K × 16 Secure Code Security Module HR

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ARM Microcontrollers - MCU Ultra-low-power Arm Cortex-M0+ MCU 16-Kbytes of Flash , 32 MHz CPUSTM32L011x3 STM32L011x4 Access line ultra-low-power 32-bit MCU Arm®-based Cortex®-M0+, up to 16KB Flash, 2KB SRAM, 512B EEPROM, ADC Datasheet - production data Features • Ultra-low-power platform – 1.65 V to 3.6 V power supply – -40 to 125 °C temperature range – 0.23 µA Standby mode (2 wakeup pins) – 0.29 µA Stop mode (16 wakeup lines) – 0.54 µA Stop mode + RTC + 2 KB RAM retention – Down to 76 µA/MHz in Run mode – 5 µs wakeup time (from Flash memory) – 41 µA 12-bit ADC conversion at 10 ksps • Core: Arm® 32-bit Cortex®-M0+ – From 32 kHz to 32 MHz max. – 0.95 DMIPS/MHz • Reset and supply management – Ultra-safe, low-power BOR (brownout reset) with 5 selectable thresholds – Ultralow power POR/PDR – Programmable voltage detector (PVD) • Clock sources – 0 to 32 MHz external clock – 32 kHz oscillator for RTC with calibration – High speed internal 16 MHz factory-trimmed RC (+/- 1%) – Internal low-power 37 kHz RC – Internal multispeed low-power 65 kHz to 4.2 MHz RC – PLL for CPU clock • Pre-programmed bootloader – USART, SPI supported • Development support – Serial wire debug supported • Up to 28 fast I/Os (23 I/Os 5V tolerant) • Memories – Up to 16 KB Flash memory with ECC – 2 KB RAM – 512 B of data EEPROM with ECC – 20-byte backup register – Sector protection against R/W operation – • Rich Analog peripherals – 12-bit ADC 1.14 Msps up to 10 channels (down to 1.65 V) – 2x ultra-low-power comparators (window mode and wake up capability, down to 1.65 V) • 5-channel DMA controller, supporting ADC, SPI, I2C, USART, Timers • 4x peripherals communication interface • 1x USART (ISO 7816, IrDA), 1x UART (low power) • 1x SPI 16 Mbits/s • 1x I2C (SMBus/PMBus) • 7x timers: 1x 16-bit with up to 4 channels, 1x 16-bit with up to 2 channels, 1x 16-bit ultra-low-power timer, 1x SysTick, 1x RTC and 2x watchdogs (independent/window) • CRC calculation unit, 96-bit unique ID • All packages are ECOPACK®2 Table 1. Device summary Reference Part number STM32L011x3 STM32L011G3, STM32L011K3, STM32L011E3, STM32L011F3, STM32L011D3 STM32L011x4 STM32L011G4, STM32L011K4, STM32L011E4, STM32L011F4, STM32L011D4 UFQFPN20 3x3 mm UFQFPN28 4x4 mm UFQFPN32 5x5 mm LQFP32 7x7 mm WLCS

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STM32F103x8 STM32F103xB Medium-density performance line ARM®-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 com. interfaces Datasheet - production data Features • ARM® 32-bit Cortex®-M3 CPU Core – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division • Memories – 64 or 128 Kbytes of Flash memory – 20 Kbytes of SRAM • Clock, reset and supply management – 2.0 to 3.6 V application supply and I/Os – POR, PDR, and programmable voltage detector (PVD) – 4-to-16 MHz crystal oscillator – Internal 8 MHz factory-trimmed RC – Internal 40 kHz RC – PLL for CPU clock – 32 kHz oscillator for RTC with calibration • Low-power – Sleep, Stop and Standby modes – VBAT supply for RTC and backup registers • 2 x 12-bit, 1 µs A/D converters (up to 16 channels) – Conversion range: 0 to 3.6 V – Dual-sample and hold capability – Temperature sensor • DMA – 7-channel DMA controller – Peripherals supported: timers, ADC, SPIs, I 2Cs and USARTs • Up to 80 fast I/O ports – 26/37/51/80 I/Os, all mappable on 16 external interrupt vectors and almost all 5 V-tolerant • Debug mode – Serial wire debug (SWD) & JTAG interfaces • 7 timers – Three 16-bit timers, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input – 16-bit, motor control PWM timer with deadtime generation and emergency stop – 2 watchdog timers (Independent and Window) – SysTick timer 24-bit downcounter • Up to 9 communication interfaces – Up to 2 x I2C interfaces (SMBus/PMBus) – Up to 3 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control) – Up to 2 SPIs (18 Mbit/s) – CAN interface (2.0B Active) – USB 2.0 full-speed interface • CRC calculation unit, 96-bit unique ID • Packages are ECOPACK® Table 1. Device summary Reference Part number STM32F103x8 STM32F103C8, STM32F103R8 STM32F103V8, STM32F103T8 STM32F103xB STM32F103RB STM32F103VB, STM32F103CB, STM32F10

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W78E052DDG is a successive microcontroller unit that is fully compatible with the widely popular 8052 despite having an 8051 core. It is an 8-bit architecture based microcontroller unit that has 8 kilobytes of Flash.

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• Packaging Details: TUBE

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Medium-density performance line ARM®-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 com. interfaces Datasheet - production data Features • ARM® 32-bit Cortex®-M3 CPU Core – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access– Single-cycle multiplication and hardware division • Memories– 64 or 128 Kbytes of Flash memory– 20 Kbytes of SRAM • Clock, reset and supply management– 2.0 to 3.6 V application supply and I/Os – POR, PDR, and programmable voltage detector (PVD)– 4-to-16 MHz crystal oscillator – Internal 8 MHz factory-trimmed RC– Internal 40 kHz RC– PLL for CPU clock– 32 kHz oscillator for RTC with calibration • Low-power– Sleep, Stop and Standby modes–VBAT supply for RTC and backup registers • 2 x 12-bit, 1 µs A/D converters (up to 16 channels)– Conversion range: 0 to 3.6 V– Dual-sample and hold capability– Temperature sensor • DMA– 7-channel DMA controller – Peripherals supported: timers, ADC, SPIs, I2Cs and USARTs • Up to 80 fast I/O ports– 26/37/51/80 I/Os, all mappable on 16 external interrupt vectors and almost all 5 V-tolerant August 2015 VFQFPN36 6 × 6 mm UFQFPN48 7 × 7 mm BGA100 10 × 10 mm UFBGA100 7 x 7 mm BGA64 5 × 5 mm LQFP100 14 × 14 mm LQFP64 10 × 10 mm  (SMBus/PMBus)– Up to 3 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control)– Up to 2 SPIs (18 Mbit/s)– CAN interface (2.0B Active)– USB 2.0 full-speed interface • CRC calculation unit, 96-bit unique ID • Packages are ECOPACK® Table 1. Device summary Reference Part number STM32F103x8 STM32F103C8, STM32F103R8 STM32F103V8, STM32F103T8 STM32F103xB STM32F103RB STM32F103VB, STM32F103CB, STM32F103TB

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ARM®-based Cortex®-M7 32b MCU+FPU, 462DMIPS, up to 1MB Flash/320+16+ 4KB RAM, crypto, USB OTG HS/FS, ethernet, 18 TIMs, 3 ADCs, 25 com itf, cam & LCD Datasheet - production data Features • Core: ARM® 32-bit Cortex®-M7 CPU with FPU, adaptive real-time accelerator (ART Accelerator™) and L1-cache: 4KB data cache and 4KB instruction cache, allowing 0-wait state execution from embedded Flash memory and external memories, frequency up to 216 MHz, MPU, 462 DMIPS/2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions. • Memories– Up to 1MB of Flash memory– 1024 bytes of OTP memory– SRAM: 320KB (including 64KB of data TCM RAM for critical real-time data) + 16KB of instruction TCM RAM (for critical real-time routines) + 4KB of backup SRAM (available in the lowest power modes)– Flexible external memory controller with up to 32-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND memories • Dual mode Quad-SPI • LCD parallel interface, 8080/6800 modes • LCD-TFT controller up to XGA resolution with dedicated Chrom-ART Accelerator™ for enhanced graphic content creation (DMA2D) • Clock, reset and supply management– 1.7 V to 3.6 V application supply and I/Os– POR, PDR, PVD and BOR– Dedicated USB power– 4-to-26 MHz crystal oscillator– Internal 16 MHz factory-trimmed RC (1% accuracy)– 32 kHz oscillator for RTC with calibration– Internal 32 kHz RC with calibration • Low-power– Sleep, Stop and Standby modes–VBAT supply for RTC, 32×32 bit backup registers + 4KB backup SRAM • 3×12-bit, 2.4 MSPS ADC: up to 24 channels and 7.2 MSPS in triple interleaved mode • 2×12-bit D/A converters • Up to 18 timers: up to thirteen 16-bit (1x low- power 16-bit timer available in Stop mode) and two 32-bit timers, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input. All 15 timers running up to 216 MHz. 2x watchdogs, SysTick timer February 2016 LQFP100 (14x14 mm) LQFP144 (20x20 mm) LQFP176 (24x24 mm) UFBGA176 (10x10 mm) TFBGA216 (13x13 mm) WLCSP143 (4.5x5.8 mm) LQFP208 (28x28 mm) TFBGA100 (8x8 mm) • General-purpose DMA: 16-stream DMA controller with FIFOs and burst support • Debug mode– SWD & JTAG interfaces–Cortex®-M7 Trace Macrocell™ • Up to 168 I/O ports with interrupt capability– Up to 164 fast I/Os up to 108 MHz– Up to 166 5 V-tolerant I/Os • Up to 25 communication interfaces– Up to 4× I2C interfaces (SMBus/PMBus)– Up to 4 USARTs/4 UARTs (27 Mbit/s, ISO7816 interface, LIN, IrDA, modem control)– Up to 6 SPIs (up to 50 Mbit/s), 3 with muxed simplex I2S for audio class accuracy via internal audio PLL or external clock– 2 x SAIs (serial audio interface)– 2 × CANs (2.0B active) and SDMMC interface– SPDIFRX interface– HDMI-CEC • Advanced connectivity– USB 2.0 full-speed device/host/OTG controller with on-chip PHY– USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI– 10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII • 8- to 14-bit parallel camera interface up to 54 Mbyte/s • Cryptographic acceleration: hardware acceleration for AES 128, 192, 256, triple DES, HASH (MD5, SHA-1, SHA-2), and HMAC • True random number generator • CRC calculation unit • RTC: subsecond accuracy, hardware calendar • 96-bit unique ID Table 1. Device summary Reference STM32F756xx Part number STM32F756VG, STM32F756ZG, STM32F756IG, STM32F756BG, STM32F756NG

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PIC18F2620-I/SP8-bit Microcontrollers - MCU 64KB 3968 RAM 25 I/O

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• Packaging Details: ESD

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We are Stockiests of Microchip Microcontroller and all Range of ICs.
Price Ranging from Rs50-1000.

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Renesas MCUs R01DS0098EJ0180 100-MHz 32-bit RX MCU, on-chip FPU, 165 DMIPS, up to 2-MB flash memory, various communications interfaces including Ethernet MAC, full-speed USB 2.0 host/function/OTG interface, CAN, 10- & 12-bit A/D converters, RTC

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The P89C51RD2 nxp contains a non-volatile 8KB/16KB/32KB/64KB Flash program memory that is both parallel programmable and serial In-System and In-Application Programmable. In-System Programming (ISP) allows the user to download new code while the microcontroller sits in the application. In-Application Programming (IAP) means that the microcontroller fetches new program code and reprograms itself while in the system. This allows for remote programming over a modem link. A default serial loader (boot loader) program in ROM allows serial In-System programming of the Flash memory via the UART without the need for a loader in the Flash code. For In-Application Programming, the user program erases and reprograms the Flash memory by use of standard routines contained in ROM. The device supports 6-clock/12-clock mode selection by programming a Flash bit using parallel programming or In-System Programming. In addition, an SFR bit (X2) in the clock control register (CKCON) also selects between 6-clock/12-clock mode. Additionally, when in 6-clock mode, peripherals may use either 6 clocks per machine cycle or 12 clocks per machine cycle. This choice is available individually for each peripheral and is selected by bits in the CKCON register. This device is a Single-Chip 8-Bit Microcontroller manufactured in an advanced CMOS process and is a derivative of the 80C51 microcontroller family. The instruction set is 100% compatible with the 80C51 instruction set. The device also has four 8-bit I/O ports, three 16-bit timer/event counters, a multi-source, four-priority-level, nested interrupt structure, an enhanced UART and on-chip oscillator and timing circuits. The added features of the P89C51RD2 nxp make it a powerful microcontroller for applications that require pulse width modulation, high-speed I/O and up/down counting capabilities such as motor control. Key


Features:

• 80C51 Central Processing Unit
• On-chip Flash Program Memory with In-System Programming (ISP) and In-Application Programming (IAP) capability
• Boot ROM contains low level Flash programming routines for downloading via the UART
• Can be programmed by the end-user application (IAP)
• Parallel programming with 87C51 compatible hardware interface to programmer
• Supports 6-clock/12-clock mode via parallel programmer (default clock mode after ChipErase is 12-clock)
• 6-clock/12-clock mode Flash bit erasable and programmable via ISP
• 6-clock/12-clock mode programmable “on-the-fly” by SFR bit
• Peripherals (PCA, timers, UART) may use either 6-clock or 12-clock mode while the CPU is in 6-clock mode
• Speed up to 20 MHz with 6-clock cycles per machine cycle (40 MHz equivalent performance); up to 33 MHz with 12 clocks per machine cycle
• Fully static operation
• RAM expandable externally to 64 kbytes
• Four interrupt priority levels
• Seven interrupt sources
• Four 8-bit I/O ports
• Full-duplex enhanced UART
  • Framing error detection
  • Automatic address recognition
• Power control modes
  • Clock can be stopped and resumed
  • Idle mode
  • Power down mode
• Programmable clock-out pin
• Second DPTR register
• Asynchronous port reset
• Low EMI (inhibit ALE)
• Programmable Counter Array (PCA)
  • PWM
  • Capture/compare

Additional Information:

• Delivery Time: 2-3
• Packaging Details: TUBE