XILINX IC

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Zynq-7000 SoC First Generation Architecture The Zynq®-7000 family is based on the Xilinx SoC architecture. These products integrate a feature-rich dual-core or single-core ARM® Cortex™-A9 based processing system (PS) and 28 nm Xilinx programmable logic (PL) in a single device. The ARM Cortex-A9 CPUs are the heart of the PS and also include on-chip memory, external memory interfaces, and a rich set of peripheral connectivity interfaces. Processing System (PS) ARM Cortex-A9 Based Application Processor Unit (APU) • 2.5 DMIPS/MHz per CPU • CPU frequency: Up to 1 GHz • Coherent multiprocessor support • ARMv7-A architecture • TrustZone® security • Thumb®-2 instruction set • Jazelle® RCT execution Environment Architecture • NEON™ media-processing engine • Single and double precision Vector Floating Point Unit (VFPU) • CoreSight™ and Program Trace Macrocell (PTM) • Timer and Interrupts • Three watchdog timers • One global timer • Two triple-timer counters Caches • 32 KB Level 1 4-way set-associative instruction and data caches (independent for each CPU) • 512 KB 8-way set-associative Level 2 cache (shared between the CPUs) • Byte-parity support On-Chip Memory • On-chip boot ROM • 256 KB on-chip RAM (OCM) • Byte-parity support External Memory Interfaces • Multiprotocol dynamic memory controller • 16-bit or 32-bit interfaces to DDR3, DDR3L, DDR2, or LPDDR2 memories • ECC support in 16-bit mode • 1GB of address space using single rank of 8-, 16-, or 32-bit-wide memories • Static memory interfaces • 8-bit SRAM data bus with up to 64 MB support • Parallel NOR flash support • ONFI1.0 NAND flash support (1-bit ECC) • 1-bit SPI, 2-bit SPI, 4-bit SPI (quad-SPI), or two quad-SPI (8-bit) serial NOR flash 8-Channel DMA Controller • Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and scatter-gather transaction support I/O Peripherals and Interfaces • Two 10/100/1000 tri-speed Ethernet MAC peripherals with IEEE Std 802.3 and IEEE Std 1588 revision 2.0 support • Scatter-gather DMA capability • Recognition of 1588 rev. 2 PTP frames • GMII, RGMII, and SGMII interfaces • Two USB 2.0 OTG peripherals, each supporting up to 12 Endpoints • USB 2.0 compliant device IP core • Supports on-the-go, high-speed, full-speed, and low-speed modes • Intel EHCI compliant USB host • 8-bit ULPI external PHY interface • Two full CAN 2.0B compliant CAN bus interfaces • CAN 2.0-A and CAN 2.0-B and ISO 118981-1 standard compliant • External PHY interface • Two SD/SDIO 2.0/MMC3.31 compliant controllers • Two full-duplex SPI ports with three peripheral chip selects • Two high-speed UARTs (up to 1 Mb/s) • Two master and slave I2C interfaces • GPIO with four 32-bit banks, of which up to 54 bits can be used with the PS I/O (one bank of 32b and one bank of 22b) and up to 64 bits (up to two banks of 32b) connected to the Programmable Logic • Up to 54 flexible multiplexed I/O (MIO) for peripheral pin assignments Interconnect • High-bandwidth connectivity within PS and between PS and PL • ARM AMBA® AXI based • QoS support on critical masters for latency and bandwidth control Zynq-7000 SoC Data Sheet: Overview DS190 (v1.11.1) July 2, 2018 Product Specification Zynq-7000 SoC Data Sheet: Overview DS190 (v1.11.1) July 2, 2018 www.xilinx.com Product Specification 2 Programmable Logic (PL) Configurable Logic Blocks (CLB) • Look-up tables (LUT) • Flip-flops • Cascadeable adders 36 Kb Block RAM • True Dual-Port • Up to 72 bits wide • Configurable as dual 18 Kb block RAM DSP Blocks • 18 x 25 signed multiply • 48-bit adder/accumulator • 25-bit pre-adder Programmable I/O

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Summary of Spartan-6 FPGA Features:
Spartan-6 Family: 

• Spartan-6 LX FPGA: Logic optimized 
• Spartan-6 LXT FPGA: High-speed serial connectivity 
• Designed for low cost
• Multiple efficient integrated blocks 
• Optimized selection of I/O standards 
• Staggered pads 
• High-volume plastic wire-bonded packages
• Low static and dynamic power 
• 45 nm  Maximum Available I/Os Package CPG196(1) TQG144(1) CSG225(2) FT(G)256(3) CSG324 FG(G)484(3,4) CSG484(4) FG(G)676(3) FG(G)900(3) 
• Body Size (mm) 8 x 8, 20 x 20, 13 x 13, 17 x 17, 15 x 15, 23 x 23, 19 x 19, 27 x 27, 31 x 31 Pitch (mm) 0.5, 0.8, 1.0, 0.8, 1.0, 0.8, 1.0 Device User I/O User I/O User I/O User I/O GTPs User I/O GTPs User I/O GTPs User I/O GTPs User I/O GTPs User I/O XC6SLX4 106 102 132 XC6SLX9 106 102 160 186 NA 200 XC6SLX16 106 160 186 NA 232 XC6SLX25 186 NA 226 NA 266 XC6SLX45 NA 218 NA 316 NA 320 NA 358 XC6SLX75 NA 280 NA 328 NA 408 XC6SLX100 NA 326 NA 338 NA 480 XC6SLX150 NA 338 NA 338 NA 498 NA 576 XC6SLX25T 2 190 2 250 XC6SLX45T 4 190 4 296 4 296 XC6SLX75T 4 268 4 292 8 348 XC6SLX100T 4 296 4 296 8 376 8 498 XC6SLX150T 4 296 4 296 8 396 8 540.

Notes: 

• There is no memory controller on the devices in these packages. 
• Memory controller block support is x8 on the XC6SLX9 and XC6SLX16 devices in the CSG225 package. There is no memory controller in the XC6SLX4. 
• These devices are available in both Pb and Pb-free (additional G) packages as standard ordering options.
• These packages support two of the four memory controllers in the XC6SLX75, XC6SLX75T, XC6SLX100, XC6SLX100T, XC.

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Zynq-7000 SoC (Z-7030, Z-7035, Z-7045, and Z-7100): DC and AC Switching Characteristics
Introduction The Zynq®-7000 SoCs are available in -3, -2, -2LI, -1, and -1LQ speed grades, with -3 having the highest performance. The -2LI devices operate at programmable logic (PL) VCCINT/VCCBRAM = 0.95V and are screened for lower maximum static power. The speed specification of a -2LI device is the same as that of a -2 device. The -1LQ devices operate at the same voltage and speed as the -1Q devices and are screened for lower power. Zynq-7000 device DC and AC characteristics are specified in commercial, extended, industrial, and expanded (Q-temp) temperature ranges. However, only selected speed grades and/or devices are available in the commercial, extended, or industrial temperature ranges. All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters included are common to popular designs and typical applications. The available device/package combinations are outlined in: • Zynq-7000 SoC Overview (DS190 ) • Defense-grade Zynq-7000Q SoC Overview (DS196 • XAZynq-7000 SoC Overview (DS188 ) ) This Zynq-7000 SoC data sheet, which covers the specifications for the XC7Z030, XA7Z030, XQ7Z030, XC7Z035, XC7Z045, XQ7Z045, XC7Z100, and XQ7Z100 complements the Zynq-7000 SoC documentation suite available on the Xilinx website at www.xilinx.com/zynq .

Xilinx:  XC7Z100-L2FFG900I  XC7Z100-2FFG900I4529  XC7Z030-1FBG484CES9919  XC7Z045-1FFG900I4358  XC7Z0302SBG485E4407  XC7Z030-L2FBG484I  XC7Z100-2FFG900I4507  XC7Z100-1FFG900I  XC7Z045-2FFG900I4469 XC7Z045-3FFV676E4400  XC7Z035-2FFV900E  XC7Z030-1FFG676CES9919  XC7Z035-3FFV900E  XC7Z100L2FFV1156I  XC7Z035-1FBV676I  XC7Z030-1FBG676C  XC7Z045-1FFV676I  XC7Z035-L2FBG676I  XC7Z0301FBV676C  XC7Z035-1FFV900I  XC7Z045-1FFG676C  XC7Z035-2FBG676I  XC7Z030-DIE4378  XC7Z045-1FBG676C XC7Z100-1FFG1156I  XC7Z030-2FF676I  XC7Z035-1FFG676I  XC7Z035-1FBV676CES9919  XC7Z035-2FBG676E XC7Z045-2FFG900E  XC7Z035-2FFV676E4400  XC7Z100-1FFV900I  XC7Z030-3FBV484E  XC7Z030-L2SBG485I XC7Z035-L2FFV676I  XC7Z035-2FFG900I4427  XC7Z045-2FFG900I4394  XC7Z045-1FFG900I  XC7Z0301SBV485CES9919  XC7Z035-2FFG900I  XC7Z045-2FBG676E  XC7Z045-1FFG900I4306  XC7Z1002FFG1156CES9919  XC7Z045-2FFG900I4529  XC7Z035-1FFV676CES9919  XC7Z045-1FFG900I4529  XC7Z0301FBG484C  XC7Z045-2FFV676E  XC7Z045-1FFV900C  XC7Z030-1FBV484CES9919  XC7Z045-1FFV900I4400 XC7Z045-1FBV676C  XC7Z035-L2FFG900I4526  XC7Z100-2FFG900I0882  XC7Z035-1FFG676C  XC7Z0303FFV676E4400  XC7Z035-2FBV676E  XC7Z045-3FBG676E  XC7Z030-1SBG485I4360  XC7Z045-2FFG676E XC7Z030-L2FBV484I  XC7Z045-2FFG900I4526  XC7Z100-2FFG1156I  XC7Z045-1FBV676I  XC7Z035-2FFG900I4487 XC7Z045-1FFG900I4357  XC7Z030-2FBG484E4755  XC7Z035-1FFV676I  XC7Z035-1FBG676I4526  XC7Z0452FBV676E  XC7Z100-2FFG900I4376  XC7Z030-3FFG676E  XC7Z045-1FFG900I4729  XC7Z100-2FFV1156I4400 XC7Z045-2FFV900I  XC7Z030-2SBG485I  XC7Z045-2FF676E  XC7Z030-DIE4415  XC7Z030-3FBG484E  XC7Z1002FFG900I4413  XC7Z030-L2FBG676I4480  XC7Z030-1SBV485I  XC7Z030-2FBV676E4400  XC7Z0451FFG900CES9919  XC7Z100-2FFV1156I  XC7Z045-L2FFV676I  XC7Z030-1SBV485C  XC7Z030-1FFG676C XC7Z045-1FFG676I  XC7Z030-1FBG676I0880  XC7Z035-2FFG900E  XC7Z030-2FBG484E  XC7Z045-2FF676I XC7Z035-2FFG676E4596  XC7Z030-2FBG676I  XC7Z030-1FBG676I  XC7Z030-1FBG676CES9919  XC7Z035L2FFV900I  XC7Z100-2FFG900I4430  XC7Z030-3FBV676E4400

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Xilinx:  XC7Z100-L2FFG900I  XC7Z100-2FFG900I4529  XC7Z030-1FBG484CES9919  XC7Z045-1FFG900I4358  XC7Z0302SBG485E4407  XC7Z030-L2FBG484I  XC7Z100-2FFG900I4507  XC7Z100-1FFG900I  XC7Z045-2FFG900I4469 XC7Z045-3FFV676E4400  XC7Z035-2FFV900E  XC7Z030-1FFG676CES9919  XC7Z035-3FFV900E  XC7Z100L2FFV1156I  XC7Z035-1FBV676I  XC7Z030-1FBG676C  XC7Z045-1FFV676I  XC7Z035-L2FBG676I  XC7Z0301FBV676C  XC7Z035-1FFV900I  XC7Z045-1FFG676C  XC7Z035-2FBG676I  XC7Z030-DIE4378  XC7Z045-1FBG676C XC7Z100-1FFG1156I  XC7Z030-2FF676I  XC7Z035-1FFG676I  XC7Z035-1FBV676CES9919  XC7Z035-2FBG676E XC7Z045-2FFG900E  XC7Z035-2FFV676E4400  XC7Z100-1FFV900I  XC7Z030-3FBV484E  XC7Z030-L2SBG485I XC7Z035-L2FFV676I  XC7Z035-2FFG900I4427  XC7Z045-2FFG900I4394  XC7Z045-1FFG900I  XC7Z0301SBV485CES9919  XC7Z035-2FFG900I  XC7Z045-2FBG676E  XC7Z045-1FFG900I4306  XC7Z1002FFG1156CES9919  XC7Z045-2FFG900I4529  XC7Z035-1FFV676CES9919  XC7Z045-1FFG900I4529  XC7Z0301FBG484C  XC7Z045-2FFV676E  XC7Z045-1FFV900C  XC7Z030-1FBV484CES9919  XC7Z045-1FFV900I4400 XC7Z045-1FBV676C  XC7Z035-L2FFG900I4526  XC7Z100-2FFG900I0882  XC7Z035-1FFG676C  XC7Z0303FFV676E4400  XC7Z035-2FBV676E  XC7Z045-3FBG676E  XC7Z030-1SBG485I4360  XC7Z045-2FFG676E XC7Z030-L2FBV484I  XC7Z045-2FFG900I4526  XC7Z100-2FFG1156I  XC7Z045-1FBV676I  XC7Z035-2FFG900I4487 XC7Z045-1FFG900I4357  XC7Z030-2FBG484E4755  XC7Z035-1FFV676I  XC7Z035-1FBG676I4526  XC7Z0452FBV676E  XC7Z100-2FFG900I4376  XC7Z030-3FFG676E  XC7Z045-1FFG900I4729  XC7Z100-2FFV1156I4400 XC7Z045-2FFV900I  XC7Z030-2SBG485I  XC7Z045-2FF676E  XC7Z030-DIE4415  XC7Z030-3FBG484E  XC7Z1002FFG900I4413  XC7Z030-L2FBG676I4480  XC7Z030-1SBV485I  XC7Z030-2FBV676E4400  XC7Z0451FFG900CES9919  XC7Z100-2FFV1156I  XC7Z045-L2FFV676I  XC7Z030-1SBV485C  XC7Z030-1FFG676C XC7Z045-1FFG676I  XC7Z030-1FBG676I0880  XC7Z035-2FFG900E  XC7Z030-2FBG484E  XC7Z045-2FF676I XC7Z035-2FFG676E4596  XC7Z030-2FBG676I  XC7Z030-1FBG676I  XC7Z030-1FBG676CES9919  XC7Z035L2FFV900I  XC7Z100-2FFG900I4430  XC7Z030-3FBV676E4400

Service Details:

The Zynq®-7000 SoCs are available in -3, -2, -2LI, -1, and -1LQ speed grades, with -3 having the highest performance. The -2LI devices operate at programmable logic (PL) VCCINT/VCCBRAM = 0.95V and are screened for lower maximum static power. The speed specification of a -2LI device is the same as that of a -2 device. The -1LQ devices operate at the same voltage and speed as the -1Q devices and are screened for lower power. Zynq-7000 device DC and AC characteristics are specified in commercial, extended, industrial, and expanded (Q-temp) temperature ranges. Except the operating temperature range or  Defense-grade Zynq-7000Q SoC Overview (DS196 • XAZynq-7000 SoC Overview (DS188 ) ) This Zynq-7000 SoC data sheet, which covers the specifications for the XC7Z030, XA7Z030, XQ7Z030, XC7Z035, XC7Z045, XQ7Z045, XC7Z100, and XQ7Z100 complements the Zynq-7000 SoC documentation suite available on the Xilinx website at www.xilinx.com/zynq . D Description Min–0.5 Max 1.1 Units VCCPAUX VCCPLL VCCO_DDR VCCO_MIO(2) VPREF VPIN(2)(3)(4)(5) PS auxiliary supply voltage PS PLL supply PS DDR I/O supply PS MIO I/O supply PS input reference voltage PS MIO I/O input voltage–0.5–0.5–0.5–0.5–0.5–0.40 2.0 2.0 2.0 3.6 2.0 V V V V V V VCCO_MIO +0.55 V PS DDR I/O i +0.55 V 1.1 1.1 2.0 3.6 2.0 2.06 V XC7Z100-L2FFG900I  XC7Z100-2FFG900I4529  XC7Z030-1FBG484CES9919  XC7Z045-1FFG900I4358  XC7Z0302SBG485E4407  XC7Z030-L2FBG484I  XC7Z100-2FFG900I4507  XC7Z100-1FFG900I  XC7Z045-2FFG900I4469 XC7Z045-3FFV676E4400  XC7Z035-2FFV900E  XC7Z030-1FFG676CES9919  XC7Z035-3FFV900E  XC7Z100L2FFV1156I  XC7Z035-1FBV676I  XC7Z030-1FBG676C  XC7Z045-1FFV676I  XC7Z035-L2FBG676I  XC7Z0301FBV676C  XC7Z035-1FFV900I  XC7Z045-1FFG676C  XC7Z035-2FBG676I  XC7Z030-DIE4378  XC7Z045-1FBG676C XC7Z100-1FFG1156I  XC7Z030-2FF676I  XC7Z035-1FFG676I  XC7Z035-1FBV676CES9919  XC7Z035-2FBG676E XC7Z045-2FFG900E  XC7Z035-2FFV676E4400  XC7Z100-1FFV900I  XC7Z030-3FBV484E  XC7Z030-L2SBG485I XC7Z035-L2FFV676I  XC7Z035-2FFG900I4427  XC7Z045-2FFG900I4394  XC7Z045-1FFG900I  XC7Z0301SBV485CES9919  XC7Z035-2FFG900I  XC7Z045-2FBG676E  XC7Z045-1FFG900I4306  XC7Z1002FFG1156CES9919  XC7Z045-2FFG900I4529  XC7Z035-1FFV676CES9919  XC7Z045-1FFG900I4529  XC7Z0301FBG484C  XC7Z045-2FFV676E  XC7Z045-1FFV900C  XC7Z030-1FBV484CES9919  XC7Z045-1FFV900I4400 XC7Z045-1FBV676C  XC7Z035-L2FFG900I4526  XC7Z100-2FFG900I0882  XC7Z035-1FFG676C  XC7Z0303FFV676E4400  XC7Z035-2FBV676E  XC7Z045-3FBG676E  XC7Z030-1SBG485I4360  XC7Z045-2FFG676E XC7Z030-L2FBV484I  XC7Z045-2FFG900I4526  XC7Z100-2FFG1156I  XC7Z045-1FBV676I  XC7Z035-2FFG900I4487 XC7Z045-1FFG900I4357  XC7Z030-2FBG484E4755  XC7Z035-1FFV676I  XC7Z035-1FBG676I4526  XC7Z0452FBV676E  XC7Z100-2FFG900I4376  XC7Z030-3FFG676E  XC7Z045-1FFG900I4729  XC7Z100-2FFV1156I4400 XC7Z045-2FFV900I  XC7Z030-2SBG485I  XC7Z045-2FF676E  XC7Z030-DIE4415  XC7Z030-3FBG484E  XC7Z1002FFG900I4413  XC7Z030-L2FBG676I4480  XC7Z030-1SBV485I  XC7Z030-2FBV676E4400  XC7Z0451FFG900CES9919  XC7Z100-2FFV1156I  XC7Z045-L2FFV676I  XC7Z030-1SBV485C  XC7Z030-1FFG676C XC7Z045-1FFG676I  XC7Z030-1FBG676I0880  XC7Z035-2FFG900E  XC7Z030-2FBG484E  XC7Z045-2FF676I XC7Z035-2FFG676E4596  XC7Z030-2FBG676I  XC7Z030-1FBG676I  XC7Z030-1FBG676CES9919  XC7Z035L2FFV900I  XC7Z100-2FFG900I4430  XC7Z030-3FBV676E4400

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General Description Xilinx® 7 series FPGAs comprise four FPGA families that address the complete range of system requirements, ranging from low cost, small form factor, cost-sensitive, high-volume applications to ultra high-end connectivity bandwidth, logic capacity, and signal processing capability for the most demanding high-performance applications. The 7 series FPGAs include: • Spartan®-7 Family: Optimized for low cost, lowest power, and high I/O performance. Available in low-cost, very small form-factor packaging for smallest PCB footprint. • Artix®-7 Family: Optimized for low power applications requiring serial transceivers and high DSP and logic throughput. Provides the lowest total bill of materials cost for high-throughput, cost-sensitive applications. • Kintex®-7 Family: Optimized for best price-performance with a 2X improvement compared to previous generation, enabling a new class of FPGAs. • Virtex®-7 Family: Optimized for highest system performance and capacity with a 2X improvement in system performance. Highest capability devices enabled by stacked silicon interconnect (SSI) technology. Built on a state-of-the-art, high-performance, low-power (HPL), 28 nm, high-k metal gate (HKMG) process technology, 7 series FPGAs enable an unparalleled increase in system performance with 2.9 Tb/s of I/O bandwidth, 2 million logic cell capacity, and 5.3 TMAC/s DSP, while consuming 50% less power than previous generation devices to offer a fully programmable alternative to ASSPs and ASICs. Summary of 7 Series FPGA Features • Advanced high-performance FPGA logic based on real 6-input lookup table (LUT) technology configurable as distributed memory. • 36Kb dual-port block RAM with built-in FIFO logic for on-chip data buffering. • High-performance SelectIO™ technology with support for DDR3 interfaces up to 1,866 Mb/s. • High-speed serial connectivity with built-in multi-gigabit transceivers from 600 Mb/s to max. rates of 6.6 Gb/s up to 28.05 Gb/s, offering a special low-power mode, optimized for chip-to-chip interfaces. • A user configurable analog interface (XADC), incorporating dual 12-bit 1MSPS analog-to-digital converters with on-chip thermal and supply sensors. • DSP slices with 25 x 18 multiplier, 48-bit accumulator, and pre-adder for high-performance filtering, including optimized symmetric coefficient filtering. Table  1: 7 Series Families Comparison Max. Capability Logic Cells Spartan-7 102K Artix-7 215K • Powerful clock management tiles (CMT), combining phase-locked loop (PLL) and mixed-mode clock manager (MMCM) blocks for high precision and low jitter. • Quickly deploy embedded processing with MicroBlaze™ processor. • Integrated block for PCI Express® (PCIe), for up to x8 Gen3 Endpoint and Root Port designs. • Wide variety of configuration options,  process, 1.0V core voltage process technology and 0.9V core voltage option for even lower power. Kintex-7 478K Virtex-7 1,955K Block RAM(1) DSP Slices DSP Performance(2) MicroBlaze CPU(3) Transceivers Transceiver Speed Serial Bandwidth PCIe Interface Memory Interface I/O Pins I/O Voltage Package Options Notes: 1. 4.2Mb 160 176 GMAC/s 260 DMIPs–––– 800 Mb/s 400 1.2V–3.3V Low-Cost, Wire-Bond Additional memory available in XC7K70T-3E (1.0V)-2C (1.0V)-2I (1.0V)-2LE (1.0V or 0.9V)-1C (1.0V)-1I (1.0V) XC7K160T XC7K325T XC7K355T XC7K410T XC7K420T XC7K480T-3E (1.0V)-2C (1.0V)-2I (1.0V)-2LE (1.0V or 0.9V)-2LI (0.95V)-1C (1.0V)-1I (1.0V) Virtex-7 T XC7V585T-3E (1.0V)-2C (1.0V)-2I (1.0V)-2LE (1.0V)-1C (1.0V)-1I (1.0V) XC7V2000T-2C (1.0V)-2GE (1.0V)-2LE (1.0V)-1C (1.0V)-1I (1.0V) Virtex-7 XT XC7VX330T XC7VX415T XC7VX485T XC7VX550T XC7VX690T-3E (1.0V)-2C (1.0V)-2I (1.0V)-2LE (1.0V)-1C (1.0V)-1I (1.0V) XC7VX980T-2C (1.0V)-2LE (1.0V)-1C (1.0V)-1I (1.0V) XC7VX1140T-2C (1.0V)-

Service Details:

The Zynq®-7000 SoCs are available in -3, -2, -2LI, -1, and -1LQ speed grades, with -3 having the highest performance. The -2LI devices operate at programmable logic (PL) VCCINT/VCCBRAM = 0.95V and are screened for lower maximum static power. The speed specification of a -2LI device is the same as that of a -2 device. The -1LQ devices operate at the same voltage and speed as the -1Q devices and are screened for lower power. Zynq-7000 device DC and AC characteristics are specified in commercial, extended, industrial, and expanded (Q-temp) temperature ranges. Except the operating temperature 

XC7Z100-L2FFG900I  XC7Z100-2FFG900I4529  XC7Z030-1FBG484CES9919  XC7Z045-1FFG900I4358  XC7Z0302SBG485E4407  XC7Z030-L2FBG484I  XC7Z100-2FFG900I4507  XC7Z100-1FFG900I  XC7Z045-2FFG900I4469 XC7Z045-3FFV676E4400  XC7Z035-2FFV900E  XC7Z030-1FFG676CES9919  XC7Z035-3FFV900E  XC7Z100L2FFV1156I  XC7Z035-1FBV676I  XC7Z030-1FBG676C  XC7Z045-1FFV676I  XC7Z035-L2FBG676I  XC7Z0301FBV676C  XC7Z035-1FFV900I  XC7Z045-1FFG676C  XC7Z035-2FBG676I  XC7Z030-DIE4378  XC7Z045-1FBG676C XC7Z100-1FFG1156I  XC7Z030-2FF676I  XC7Z035-1FFG676I  XC7Z035-1FBV676CES9919  XC7Z035-2FBG676E XC7Z045-2FFG900E  XC7Z035-2FFV676E4400  XC7Z100-1FFV900I  XC7Z030-3FBV484E  XC7Z030-L2SBG485I XC7Z035-L2FFV676I  XC7Z035-2FFG900I4427  XC7Z045-2FFG900I4394  XC7Z045-1FFG900I  XC7Z0301SBV485CES9919  XC7Z035-2FFG900I  XC7Z045-2FBG676E  XC7Z045-1FFG900I4306  XC7Z1002FFG1156CES9919  XC7Z045-2FFG900I4529  XC7Z035-1FFV676CES9919  XC7Z045-1FFG900I4529  XC7Z0301FBG484C  XC7Z045-2FFV676E  XC7Z045-1FFV900C  XC7Z030-1FBV484CES9919  XC7Z045-1FFV900I4400 XC7Z045-1FBV676C  XC7Z035-L2FFG900I4526  XC7Z100-2FFG900I0882  XC7Z035-1FFG676C  XC7Z0303FFV676E4400  XC7Z035-2FBV676E  XC7Z045-3FBG676E  XC7Z030-1SBG485I4360  XC7Z045-2FFG676E XC7Z030-L2FBV484I  XC7Z045-2FFG900I4526  XC7Z100-2FFG1156I  XC7Z045-1FBV676I  XC7Z035-2FFG900I4487 XC7Z045-1FFG900I4357  XC7Z030-2FBG484E4755  XC7Z035-1FFV676I  XC7Z035-1FBG676I4526  XC7Z0452FBV676E  XC7Z100-2FFG900I4376  XC7Z030-3FFG676E  XC7Z045-1FFG900I4729  XC7Z100-2FFV1156I4400 XC7Z045-2FFV900I  XC7Z030-2SBG485I  XC7Z045-2FF676E  XC7Z030-DIE4415  XC7Z030-3FBG484E  XC7Z1002FFG900I4413  XC7Z030-L2FBG676I4480  XC7Z030-1SBV485I  XC7Z030-2FBV676E4400  XC7Z0451FFG900CES9919  XC7Z100-2FFV1156I  XC7Z045-L2FFV676I  XC7Z030-1SBV485C  XC7Z030-1FFG676C XC7Z045-1FFG676I  XC7Z030-1FBG676I0880  XC7Z035-2FFG900E  XC7Z030-2FBG484E  XC7Z045-2FF676I XC7Z035-2FFG676E4596  XC7Z030-2FBG676I  XC7Z030-1FBG676I  XC7Z030-1FBG676CES9919  XC7Z035L2FFV900I  XC7Z100-2FFG900I4430  XC7Z030-3FBV676E4400

Service Details:

Features • 5 ns pin-to-pin logic delays • System frequency up to 178 MHz • 144 macrocells with 3,200 usable gates • Available in small footprint packages- 100-pin TQFP (81 user I/O pins)--- 144-pin TQFP (117 user I/O pins) 144-CSP (117 user I/O pins) Pb-free available for all packages • Optimized for high-performance 3.3V systems- Low power operation--- 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals 3.3V or 2.5V output capability Advanced 0.35 micron feature size CMOS Fast FLASH™ technology • Advanced system features- In-system programmable-------- Superior pin-locking and routability with Fast CONNECT™ II switch matrix Extra wide 54-input Function Blocks Up to 90 product-terms per macrocell with individual product-term allocation Local clock inversion with three global and one product-term clocks Individual output enable per output pin with local inversion Input hysteresis on all user and boundary-scan pin inputs Bus-hold circuitry on all user pin inputs Full IEEE Standard 1149.1 boundary-scan (JTAG) • Fast concurrent programming • Slew rate control on individual outputs • Enhanced data security features • Excellent quality and reliability - Endurance exceeding 10,000 program/erase cycles-- 20 year data retention ESD protection exceeding 2,000V • Pin-compatible with 5V-core XC95144 device in the 100-pin TQFP package WARNING: Programming temperature range of TA = 0° C to +70° C Description The XC95144XL is a 3.3V CPLD targeted for high-performance, low-voltage applications in leading-edge communications and computing systems. It is comprised of eight 54V18 Function Blocks, providing 3,200 usable gates with propagation delays of 5 ns. See Figure 2 for overview. Power Estimation Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell in a XC9500XL device may be configured for low-power mode  +MCLP)* f where: MCHS = # macrocells in high-speed configuration PTHS = average number of high-speed product terms per macrocell MCLP = # macrocells in low power configuration PTLP = average number of low power product terms per macrocell f = maximum clock frequency MCTOG = average % of flip-flops toggling per clock (~12%) This calculation was derived from laboratory measurements of an XC9500XL part filled with 16-bit counters and allowing a single output (the LSB) to be enabled. The actual ICC value varies with the design application and should be verified during normal system operation. Figure 1 shows the above estimation in a graphical form. For a more detailed discussion of power consumption in this device, see XilinxXC95144XL-5CS144C  XC95144XL-7TQ144I0962  XC95144XL-10TQ144C0962  XC95144XL-10CSG144I XC95144XL-10TQ144C  XC95144XL-10TQ144I0952  XC95144XL-7TQ100C  XC95144XL-10TQG100C  XC95144XL10TQ100I0962  XC95144XL-10CSG144C  XC95144XL-7CS144I  XC95144XL-7CSG144I  XC95144XL-7TQ144I XC95144XL-5TQG100C  XC95144XL-10CS144I  XC95144XL-10TQ100I  XC95144XL-10TQ100C0962  XC95144XL7TQ100I  XC95144XL-10CS144C  XC95144XL-7CSG144C  XC95144XL-5TQ100C0962  XC95144XL-7TQ144C0962 XC95144XL-10TQ144I4766  XC95144XL-5TQG144C  XC95144XL-5TQ100C  XC95144XL-10TQ100C  XC95144XL10TQ100I4766  XC95144XL-10TQG100C4117  XC95144XL-7TQG100I  XC95144XL-10TQG100I  XC95144XL10TQ144I  XC95144XL-10TQG144I  XC95144XL-7TQG144C  XC95144XL-5CSG144C  XC95144XL-7TQG144I XC95144XL-7TQ100C0962  XC95144XL-7CS144C  XC95144XL-10TQG144C  XC95144XL-7TQ144C  XC95144XL7TQG100C  XC95144XL-5TQ144C  XC95144XL-10TQ144I0962  XC95144XL-5TQ144C0962  XC95144XL10TQ144C4766

Service Details:

General Description Xilinx® 7 series FPGAs comprise four FPGA families that address the complete range of system requirements, ranging from low cost, small form factor, cost-sensitive, high-volume applications to ultra high-end connectivity bandwidth, logic capacity, and signal processing capability for the most demanding high-performance applications. compared to previous generation, enabling a new class of FPGAs. • Virtex®-7 Family: Optimized for highest system performance and capacity with a 2X improvement in system performance. Highest capability devices enabled by stacked silicon interconnect (SSI) technology. Built on a state-of-the-art, high-performance, low-power (HPL), 28 nm, high-k metal gate (HKMG) process technology, 7 series FPGAs enable an unparalleled increase in system performance with 2.9 Tb/s of I/O bandwidth, 2 million logic cell capacity, and 5.3 TMAC/s DSP, while consuming 50% less power than previous generation devices to offer a fully programmable alternative to ASSPs and ASICs. Summary of 7 Series FPGA Features • Advanced high-performance FPGA logic based on real 6-input lookup table (LUT) technology configurable as distributed memory. • 36Kb dual-port block RAM with built-in FIFO logic for on-chip data buffering. • High-performance SelectIO™ technology with support for DDR3 interfaces up to 1,866 Mb/s. • High-speed serial connectivity with built-
XC7K325T-1FF676I  XC7K325T-2FFG900C  XC7K325T-3FFG676E  XC7K325T-L2FFG900I  XC7K410T-1FBG900I XC7K160T-L2FBG484E  XC7VX980T-1FF1926I4570  XC7VX690T-L2FF1158E  XC7VX980T-L2FF1930E  XC7VH870TL2FL1932E  XC7VX1140T-L2FLG1926E4533  XC7VX1140T-L2FLG1928E4533  XC7VX330T-L2FFV1157E XC7VX415T-1FFV1157C  XC7VX415T-2FFV1158I4400  XC7K70T-1FBG676I4526  XC7K70T-2FBV676C  XC7K70T2FBV676I  XC7V2000T-L2FH1761E  XC7VH580T-2HC1155C  XC7VH580T-G2FL1155E  XC7K410T-3FB676E XC7K410T-L2FFG900E4607  XC7K410T-L2FFV676E  XC7K420T-2FF1156C  XC7K480T-2FFG901I4409  XC7K70T1FBG676CES9873  XC7K325T-L2FF676E  XC7K325T-L2FFG900E4607  XC7K325T-L2FFV676I  XC7K355T2FFG901I4615  XC7K355T-2FFG901I4617  XC7K410T-1FFV900C  XC7K160T-L2FBV484E  XC7K325T1FF676CES9919  XC7K325T-1FF900C4374  XC7K325T-2FFG900I4314  XC7K325T-3FB900E  XC7K325T-3FF676E XC7K480T-1FFV1156CES9919  XC7K480T-1FFV901CES9919  XC7VX330T-1FFV1761CES9919  XC7K160T1FFG676C4695  XC7K160T-2FBV676I4400  XC7K160T-3FF676E  XC7VX485T-3FFG1158E  XC7VX485T-3FFG1930E XC7VX550T-3FFG1927E  XC7VX550T-L2FFG1158E  XC7VX690T-L2FFG1927E  XC7VX980T-L2FFG1930E XC7VH870T-1FLG1932C  XC7VX1140T-L2FLG1926E  XC7VX330T-2FFG1761C  XC7VX415T-2FFG1157I XC7VX415T-2FFG1158C  XC7VX485T-2FF1761C  XC7K410T-1FFG676I  XC7K410T-1FFG900C  XC7K410T3FBG676E  XC7K420T-2FF901I  XC7V2000T-1FHG1761I  XC7V2000T-1FL1925C  XC7K325T-2FFG900I  XC7K355T1FFG901I  XC7K355T-2FF901I  XC7K355T-2FFG901I  XC7K410T-1FF900I  XC7K410T-1FFG676C  XC7K410T1FFG676CES9919  XC7K420T-1FFV1156C4400  XC7VX485T-L2FF1761E  XC7K160T-1FB676I  XC7K160T-2FBG676I XC7K325T-1FFG900I  XC7VX415T-2FFG1158C4482  XC7VX415T-2FFG1158C4672  XC7VX415T-L2FFG1158E4310 XC7VX415T-L2FFG1158E4503  XC7VX690T-2FFG1157C4774  XC7K355T-1FFV901CES9919  XC7V2000T2FH1761C  XC7V585T-2FF1157I  XC7VH580T-L2HC1931E  XC7VX330T-2FFV1157C  XC7VX330T-3FFV1157E XC7VX415T-2FFG1157C4529  XC7K480T-1FFV1156C  XC7K480T-1FFV901C  XC7K70T-2FBG676C4526  XC7K70T3FBV676E  XC7V2000T-1FL1925I  XC7V2000T-1FLG1925C4556  XC7K325T-3FFV900E  XC7K325T-DIE4058 XC7K325T-L2FB676E  XC7K410T-L2FB900E  XC7K420T-1FF901C  XC7K420T-2FFV901I  XC7K160T-2FB484C

Service Details:

FPGA - Field Programmable Gate Array XC7A35T-1FTG256IXilinx® 7 series FPGAs comprise four FPGA families that address the complete range of system requirements, ranging from low cost, small form factor, cost-sensitive, high-volume applications to ultra high-end connectivity bandwidth, logic capacity, and signal processing capability for the most demanding high-performance applications. The 7 series FPGAs include: • Spartan®-7 Family: Optimized for low cost, lowest power, and high I/O performance. Available in low-cost, very small form-factor packaging for smallest PCB footprint. • Artix®-7 Family: Optimized for low power applications requiring serial transceivers and high DSP and logic throughput. Provides the lowest total bill of materials cost for high-throughput, cost-sensitive applications. • Kintex®-7 Family: Optimized for best price-performance with a 2X improvement compared to previous generation, enabling a new class of FPGAs. • Virtex®-7 Family: Optimized for highest system performance and capacity with a 2X improvement in system performance. Highest capability devices enabled by stacked silicon interconnect (SSI) technology. Built on a state-of-the-art, high-performance, low-power (HPL), 28 nm, high-k metal gate (HKMG) process technology, 7 series FPGAs enable an unparalleled increase in system performance with 2.9 Tb/s of I/O bandwidth, 2 million logic cell capacity, and 5.3 TMAC/s DSP, while consuming 50% less power than previous generation devices to offer a fully programmable alternative to ASSPs and ASICs. 

Service Details:

ARM Cortex-A9 Based Application Processor Unit (APU) • 2.5 DMIPS/MHz per CPU • CPU frequency: Up to 1 GHz • Coherent multiprocessor support • ARMv7-A architecture • TrustZone® security • Thumb®-2 instruction set • Jazelle® RCT execution Environment Architecture • NEON™ media-processing engine • Single and double precision Vector Floating Point Unit (VFPU) • CoreSight™ and Program Trace Macrocell (PTM) • Timer and Interrupts • Three watchdog timers • One global timer • Two triple-timer counters Caches • 32KB Level1 4-way set-associative instruction and data caches (independent for each CPU) • 512KB 8-way set-associative Level 2 cache (shared between the CPUs) • Byte-parity support On-Chip Memory • On-chip boot ROM • 256KB on-chip RAM (OCM) • Byte-parity support External Memory Interfaces • Multiprotocol dynamic memory controller • 16-bit or 32-bit interfaces to DDR3, DDR3L, DDR2, or LPDDR2 memories • ECC support in 16-bit mode • 1GB of address space using single rank of 8-, 16-, or 32-bit-wide memories • Static memory interfaces • 8-bit SRAM data bus with up to 64 MB support • Parallel NOR flash support • ONFI1.0 NAND flash support (1-bit ECC) • 1-bit SPI, 2-bit SPI, 4-bit SPI (quad-SPI), or two quad-SPI (8-bit) serial NOR flash 8-Channel DMA Controller • Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and scatter-gather transaction support I/O Peripherals and Interfaces • Two 10/100/1000 tri-speed Ethernet MAC peripherals with IEEE Std 802.3 and IEEE Std 1588 revision 2.0 support • Scatter-gather DMA capability • Recognition of 1588 rev. 2 PTP frames • GMII, RGMII, and SGMII interfaces • Two USB 2.0 OTG peripherals, each supporting up to 12 Endpoints • USB 2.0 compliant device IP core • Supports on-the-go, high-speed, full-speed, and low-speed modes • Intel EHCI compliant USB host • 8-bit ULPI external PHY interface • Two full CAN 2.0B compliant CAN bus interfaces • CAN 2.0-A and CAN 2.0-B and ISO 118981-1 standard compliant • External PHY interface • Two SD/SDIO 2.0/MMC3.31 compliant controllers • Two full-duplex SPI ports with three peripheral chip selects • Two high-speed UARTs (up to 1 Mb/s) • Two master and slave I2C interfaces • GPIO with four 32-bit banks, of which up to 54 bits can be used with the PS I/O (one bank of 32b and one bank of 22b) and up to 64 bits (up to two banks of 32b) connected to the Programmable Logic • Up to 54 flexible multiplexed I/O (MIO) for peripheral pin assignments Interconnect • High-bandwidth connectivity within PS and between PS and PL • ARM AMBA® AXI based • QoS support on critical masters for latency and bandwidth control
FPGA Zynq-7000 Family 65000 Cells 667MHz 28nm 1V 484-Pin WCBGA Tray